Semiconductor integrated circuit (IC) chips are typically tested during manufacturing to verify that they function appropriately and reliably. This is often done when the semiconductor chips are still in wafer form, that is, before they are diced from the wafer and packaged. This allows the simultaneous testing of many semiconductor chips in parallel, creating considerable advantages in cost and process time compared to testing individual chips once they are packaged. If chips are found to be defective, they may be discarded when the chips are diced from the wafer, and only the reliable chips need be packaged. Alternatively, semiconductor chips may be tested after dicing, but before packaging by assembling die on tape or a mechanical carrier.
In certain applications IC chips 100 are stacked and interconnected in three-dimensional columns 110, for instance as shown in FIG. 1. Typically, two types of process flows are used to create three-dimensional ICs. In the first typical process flow 200, shown in FIG. 2, fabrication 210 creates silicon wafers 220, which are then tested 230. After testing 230, individual dice 250 are cut or “singulated” 240, then assembled 260 into three-dimensional stacks 270. The three-dimensional stacks 270 are then tested 280. Thus, in this first process flow 200, the individual dice 250 are singulated 240 prior to assembly 260 of the dice 250 into three-dimensional columns 270.
In the second typical process flow 300, shown in FIG. 3, fabrication 310 creates silicon wafers 320, which are then tested 330. But then after testing 330, the wafers 320 are then stacked 340, and then the stacked wafers are tested 350. After the stacked wafers are tested 350, then they are cut or “singulated” 360 into individual stacked or three-dimensional columns of ICs 370, which are then tested again 280. Thus, in this second process flow 300, the three-dimensional columns 370 are singulated 360 after the wafers 320 are assembled 340.
As shown in FIGS. 2 and 3, the dies or “dice” that make up a three-dimensional IC 270, 370 are tested 230, 330 in isolation before being assembled into a three-dimensional IC 270, 370. The assembled three-dimensional ICs 270, 370 are then tested again 280, 380 at the end of the processes for a final quality determination. This current methodology of testing the assembled three-dimensional ICs 270, 370 only after they are completely assembled leads to entire three-dimensional ICs 270, 370 being deemed bad if any of the Individual ICs 100 are bad or an error is introduced during the assembly process at any step. This results in three-dimensional ICs 270, 370 tending to have high scrap rates, high repair costs, and low yields, wasting time and material.
It would be advantageous if there were a way to test the three-dimensional ICs 270, 370 as they were being assembled, in partially completed stages, to more quickly identify bad dies or processing errors that will eventually lead to the failure of a completed three-dimensional stack of ICs 270, 370. This would avoid the wasted, time effort and materials spent completing the manufacture of three-dimensional ICs 270, 370 that are doomed to fail due to a bad die or process step. However, testing of partially competed three-dimensional ICs is not done today as part of the manufacturing flow 200, 300.